Hussain et al., 2013 - Google Patents
DESIGN OF SIGNATURE REGISTERS USING SCAN FLIP-FLOPS FOR ON-CHIP DELAY MEASUREMENTHussain et al., 2013
View PDF- Document ID
- 13308518973140091938
- Author
- Hussain P
- Babu G
- Publication year
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Snippet
This paper presents a delay measurement techniques using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with …
- 238000005259 measurement 0 title abstract description 88
Classifications
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- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
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- G01R31/318555—Control logic
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- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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- G01R31/318541—Scan latches or cell details
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- G—PHYSICS
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- G—PHYSICS
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- G—PHYSICS
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- G—PHYSICS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
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