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Hussain et al., 2013 - Google Patents

DESIGN OF SIGNATURE REGISTERS USING SCAN FLIP-FLOPS FOR ON-CHIP DELAY MEASUREMENT

Hussain et al., 2013

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Document ID
13308518973140091938
Author
Hussain P
Babu G
Publication year

External Links

Snippet

This paper presents a delay measurement techniques using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with …
Continue reading at citeseerx.ist.psu.edu (PDF) (other versions)

Classifications

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    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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    • GPHYSICS
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    • GPHYSICS
    • G11INFORMATION STORAGE
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    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14Implementation of control logic, e.g. test mode decoders

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