Angizi et al., 2019 - Google Patents
Graphide: A graph processing accelerator leveraging in-dram-computingAngizi et al., 2019
View PDF- Document ID
- 13397270596016330755
- Author
- Angizi S
- Fan D
- Publication year
- Publication venue
- Proceedings of the 2019 on Great Lakes Symposium on VLSI
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Snippet
In this paper, we propose GraphiDe, a novel DRAM-based processing-in-memory (PIM) accelerator for graph processing. It transforms current DRAM architecture to massively parallel computational units exploiting the high internal bandwidth of the modern memory …
- 230000015654 memory 0 abstract description 50
Classifications
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
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- G—PHYSICS
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- G06F15/00—Digital computers in general; Data processing equipment in general
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- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
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- G—PHYSICS
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