[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Meng et al., 2023 - Google Patents

TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems

Meng et al., 2023

Document ID
13295813708868598269
Author
Meng F
Wu Y
Zhang Z
Lu W
Publication year
Publication venue
IEEE Transactions on Circuits and Systems I: Regular Papers

External Links

Snippet

Compute-in-Memory (CIM) implemented with Resistive-Random-Access-Memory (RRAM) crossbars is a promising approach for accelerating Convolutional Neural Network (CNN) computations. The growing size in the number of parameters in state-of-the-art CNN models …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G06F17/30386Retrieval requests
    • G06F17/30424Query processing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/02Computer systems based on biological models using neural network models
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/16Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/12Computer systems based on biological models using genetic models
    • G06N3/126Genetic algorithms, i.e. information processing using digital simulations of the genetic system
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass
    • G06N99/005Learning machines, i.e. computer in which a programme is changed according to experience gained by the machine itself during a complete run

Similar Documents

Publication Publication Date Title
Peng et al. DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training
Chen et al. Multiply accumulate operations in memristor crossbar arrays for analog computing
US10346347B2 (en) Field-programmable crossbar array for reconfigurable computing
Bavikadi et al. A review of in-memory computing architectures for machine learning applications
Zhang et al. Design guidelines of RRAM based neural-processing-unit: A joint device-circuit-algorithm analysis
Cai et al. Low bit-width convolutional neural network on RRAM
Chang et al. AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed
Giacomin et al. A robust digital RRAM-based convolutional block for low-power image processing and learning applications
Dutta et al. Hdnn-pim: Efficient in memory design of hyperdimensional computing with feature extraction
Chen et al. Zara: A novel zero-free dataflow accelerator for generative adversarial networks in 3d reram
Jain et al. A heterogeneous and programmable compute-in-memory accelerator architecture for analog-ai using dense 2-d mesh
Yu et al. SPRING: A sparsity-aware reduced-precision monolithic 3D CNN accelerator architecture for training and inference
Liu et al. Bit-transformer: Transforming bit-level sparsity into higher preformance in reram-based accelerator
Luo et al. AILC: Accelerate on-chip incremental learning with compute-in-memory technology
Meng et al. Exploring compute-in-memory architecture granularity for structured pruning of neural networks
Peng et al. Inference engine benchmarking across technological platforms from CMOS to RRAM
Liu et al. Era-bs: Boosting the efficiency of reram-based pim accelerator with fine-grained bit-level sparsity
Meng et al. TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems
Mikhaylov et al. Neuromorphic computing based on CMOS-integrated memristive arrays: current state and perspectives
Zhou et al. Bring memristive in-memory computing into general-purpose machine learning: A perspective
Hanif et al. Resistive crossbar-aware neural network design and optimization
Shen et al. PRAP-PIM: A weight pattern reusing aware pruning method for ReRAM-based PIM DNN accelerators
Lu et al. A runtime reconfigurable design of compute-in-memory–based hardware accelerator for deep learning inference
Liu et al. SoBS-X: Squeeze-out bit sparsity for ReRAM-crossbar-based neural network accelerator
Jang et al. In-depth survey of processing-in-memory architectures for deep neural networks