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Ganai et al., 2007 - Google Patents

Synthesizing" Verification Aware" Models: Why and How?

Ganai et al., 2007

Document ID
13134644274988446534
Author
Ganai M
Mukaiyama A
Gupta A
Wakabayshi K
Publication year
Publication venue
20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

External Links

Snippet

Design-for-verification (DFV) methodology ie, exporting designer's intent to verification tools has been quite effective in improving verification efforts. The authors take one step further in improving the verification efforts, by separating the design optimized for performance, area …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
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