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Zhang et al., 2018 - Google Patents

Efficient fixed/floating-point merged mixed-precision multiply-accumulate unit for deep learning processors

Zhang et al., 2018

Document ID
13015898846397888188
Author
Zhang H
Lee H
Ko S
Publication year
Publication venue
2018 IEEE international symposium on circuits and systems (ISCAS)

External Links

Snippet

Deep learning is getting more and more attentions in recent years. Many hardware architectures have been proposed for efficient implementation of deep neural network. The arithmetic unit, as a core processing part of the hardware architecture, can determine the …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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