[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Zhu, 2019 - Google Patents

Α New Methodology and CAD Programs to Detect Two Serious Faults in VLSI Design: HV/LV Connection Faults and Floating Gate Faults.

Zhu, 2019

View PDF
Document ID
12829269944200451164
Author
Zhu Q
Publication year
Publication venue
WSEAS Transactions on Circuits and Systems

External Links

Snippet

This paper presents the new methodology and CAD programs to detect two serious faults in VLSI design: HV/LV connection faults and floating gate faults. A hierarchical circuit netlist is flattened in order to trace the connectivity of MOS devices in hierarchically designed circuits …
Continue reading at wseas.com (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/20—Handling natural language data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning

Similar Documents

Publication Publication Date Title
US10380297B2 (en) Integrated circuit design using generation and instantiation of circuit stencils
US5717928A (en) System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description
US7949987B1 (en) Method and system for implementing abstract layout structures with parameterized cells
US11238202B2 (en) Verifying glitches in reset path using formal verification and simulation
Shepard et al. Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors
US7103862B2 (en) Method to design and verify an integrated circuit device with multiple power domains
US8010920B2 (en) Constraint management and validation for template-based circuit design
US6272665B1 (en) Method and tool for automatically generating engineering change order
US7587305B2 (en) Transistor level verilog
US6249899B1 (en) System and method for detecting pass FETs
Zhu Α New Methodology and CAD Programs to Detect Two Serious Faults in VLSI Design: HV/LV Connection Faults and Floating Gate Faults.
Kamath et al. A comprehensive multi-voltage design platform for system-level validation of standard cell library
Grundmann et al. Designing high performance CMOS microprocessors using full custom techniques
De Geus SPECS: SIMULATION PROGRAM FOR ELECTRONIC CIRCUITS AND SYSTEMS (CAD, SWITCH-LEVEL, TIMING, MOS)
Eissa et al. Parametric dfm solution for analog circuits: electrical-driven hotspot detection, analysis, and correction flow
US6718522B1 (en) Electrical rules checker system and method using tri-state logic for electrical rule checks
Dall'Ora et al. Verilog-a implementation of generic defect templates for analog fault injection
US6484296B1 (en) Electrical rules checker system and method for reporting problems with tri-state logic in electrical rules checking
Zhu Automated diagnosis of HV/LV and floating gate faults in VLSI design
Chew et al. Integrating Design for Testability Technique into OpenLane with Skywater 130-Nanometer Process Design Kit
Veigas et al. Open source VLSI design automation
US20230016865A1 (en) Diagnosis of inconsistent constraints in a power intent for an integrated circuit design
Wuerdig et al. LEX-A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization
Fox The design of high-performance microprocessors at Digital
Golson The human ECO compiler