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Reinman et al., 2001 - Google Patents

Optimizations enabled by a decoupled front-end architecture

Reinman et al., 2001

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Document ID
12877785147286466753
Author
Reinman G
Calder B
Austin T
Publication year
Publication venue
IEEE Transactions on Computers

External Links

Snippet

In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery …
Continue reading at cseweb.ucsd.edu (PDF) (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic prediction, e.g. branch history table
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    • G—PHYSICS
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