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Steinke et al., 2001 - Google Patents

Low power code generation for a RISC processor by register pipelining

Steinke et al., 2001

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Document ID
12877167968229685840
Author
Steinke S
Schwarz R
Wehmeyer L
Marwedel P
Publication year
Publication venue
Technical report, Dept. Comput. Sci. XII

External Links

Snippet

This paper presents the implementation of the compiler technique register pipelining with respect to energy optimization and its comparison against performance optimization. Generally, programs optimized for performance are also energy optimized. An exception to …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. incrementing the instruction counter, jump
    • G06F9/322—Address formation of the next instruction, e.g. incrementing the instruction counter, jump for non-sequential address
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