Kunz et al., 1994 - Google Patents
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimizationKunz et al., 1994
View PDF- Document ID
- 12042218548668395543
- Author
- Kunz W
- Pradhan D
- Publication year
- Publication venue
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
External Links
Snippet
Motivated by the problem of test pattern generation in digital circuits, this paper presents a novel technique called recursive learning that is able to perform a logic analysis on digital circuits. By recursively calling certain learning functions, it is possible to extract all logic …
- 230000013016 learning 0 title abstract description 179
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
- G01R31/31835—Analysis of test coverage or failure detectability
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequence for sequential circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318335—Test pattern compression or decompression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N5/00—Computer systems utilising knowledge based models
- G06N5/02—Knowledge representation
- G06N5/022—Knowledge engineering, knowledge acquisition
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Kunz et al. | Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization | |
Kunz et al. | Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci | |
Kunz et al. | Multi-level logic optimization by implication analysis | |
US5649165A (en) | Topology-based computer-aided design system for digital circuits and method thereof | |
Kunz | HANNIBAL: An efficient tool for logic verification based on recursive learning | |
Kelsey et al. | An efficient algorithm for sequential circuit test generation | |
Kunz et al. | Reasoning in Boolean Networks: logic synthesis and verification using testing techniques | |
Tafertshofer et al. | A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists | |
Cheng et al. | Multi-level logic optimization by redundancy addition and removal | |
US5461573A (en) | VLSI circuits designed for testability and methods for producing them | |
Tafertshofer et al. | Igraine-an implication graph-based engine for fast implication, justification, and propagation | |
Kunz et al. | Accelerated dynamic learning for test pattern generation in combinational circuits | |
Silva et al. | Dynamic search-space pruning techniques in path sensitization | |
Cho et al. | Fast sequential ATPG based on implicit state enumeration | |
US6408424B1 (en) | Verification of sequential circuits with same state encoding | |
Kunda et al. | Speed up of test generation using high-level primitives | |
Chatterjee et al. | LOT: Logic optimization with testability-new transformations using recursive learning | |
Tafertshofer et al. | SAT based ATPG using fast justification and propagation in the implication graph | |
Cox et al. | On necessary and nonconflicting assignments in algorithmic test pattern generation | |
Kanjilal et al. | Test function embedding algorithms with application to interconnected finite state machines | |
Pradhan et al. | VERILAT: Verification using logic augmentation and transformations | |
Kunz et al. | SAT and ATPG: Algorithms for boolean decision problems | |
US6378096B1 (en) | On-line partitioning for sequential circuit test generation | |
Srinivasan et al. | Algebraic ATPG of combinational circuits using binary decision diagrams | |
Bushnell et al. | A functional decomposition method for redundancy identification and test generation |