Della Sala et al., 2021 - Google Patents
A novel ultra-compact fpga puf: The dd-pufDella Sala et al., 2021
View HTML- Document ID
- 1193878518356233267
- Author
- Della Sala R
- Bellizia D
- Scotti G
- Publication year
- Publication venue
- Cryptography
External Links
Snippet
In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the …
- 230000004044 response 0 description 58
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Della Sala et al. | A novel ultra-compact fpga puf: The dd-puf | |
Nannipieri et al. | True random number generator based on Fibonacci-Galois ring oscillators for FPGA | |
Che et al. | A privacy-preserving, mutual PUF-based authentication protocol | |
Vijayakumar et al. | On improving reliability of SRAM-based physically unclonable functions | |
Rooney et al. | Creation and detection of hardware trojans using non-invasive off-the-shelf technologies | |
Della Sala et al. | A novel FPGA implementation of the NAND-PUF with minimal resource usage and high reliability | |
Cui et al. | Lightweight modeling attack-resistant multiplexer-based multi-PUF (MMPUF) design on FPGA | |
Martin et al. | Total ionizing dose effects on a delay-based physical unclonable function implemented in FPGAs | |
Martinez-Rodriguez et al. | A configurable RO-PUF for securing embedded systems implemented on programmable devices | |
Owen Jr et al. | An autonomous, self-authenticating, and self-contained secure boot process for field-programmable gate arrays | |
Gołofit et al. | Chaos-based physical unclonable functions | |
Della Sala et al. | A monostable physically unclonable function based on improved RCCMs with 0–1.56% native bit instability at 0.6–1.2 V and 0–75 C | |
Cao et al. | Entropy sources based on silicon chips: True random number generator and physical unclonable function | |
Guo et al. | Barrel shifter physical unclonable function based encryption | |
Enamul Quadir et al. | Key generation for hardware obfuscation using strong pufs | |
Martínez-Rodríguez et al. | Efficient RO-PUF for generation of identifiers and keys in resource-constrained embedded systems | |
Lata et al. | FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis | |
Rojas-Muñoz et al. | True random number generation capability of a ring oscillator PUF for reconfigurable devices | |
Plusquellic | Shift register, reconvergent-fanout (sirf) puf implementation on an fpga | |
Mestice et al. | Analysis and design of integrated blocks for a 6.25 GHz spacefibre PLL | |
Zhang et al. | A novel SRAM PUF stability improvement method using ionization irradiation | |
Serrano et al. | A Unified PUF and Crypto Core Exploiting the Metastability in Latches | |
Lee et al. | Design of resistor-capacitor physically unclonable function for resource-constrained IoT devices | |
Aparicio-Téllez et al. | Oscillator Selection Strategies to Optimize a Physically Unclonable Function for IoT Systems Security | |
Klein et al. | The cost of a true random bit—On the electronic cost gain of ASIC time-domain-based TRNGs |