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Biswas et al., 2016 - Google Patents

A 0.36 V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI

Biswas et al., 2016

Document ID
11479209252347984720
Author
Biswas A
Chandrakasan A
Publication year
Publication venue
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference

External Links

Snippet

This paper presents a low-voltage, energy-efficient SRAM designed in a 28nm fully depleted SOI (FDSOI) technology. The SRAM achieves a minimum V dd of 0.36 V, while still having the area advantage by using 6T bit-cells. Dynamic forward body-biasing (DFBB) is used to …
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Classifications

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