[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Liu et al., 2015 - Google Patents

Low cost fault-tolerant routing algorithm for networks-on-chip

Liu et al., 2015

View PDF
Document ID
11232441571371017320
Author
Liu J
Harkin J
Li Y
Maguire L
Publication year
Publication venue
Microprocessors and Microsystems

External Links

Snippet

A novel adaptive routing algorithm–Efficient Dynamic Adaptive Routing (EDAR) is proposed to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path selection mechanism. It is based on a weighted path selection strategy, which exploits the …
Continue reading at salford-repository.worktribe.com (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/22Alternate routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/12Shortest path evaluation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/06Deflection routing, e.g. hot-potato routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/28Route fault recovery
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/02Topology update or discovery
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/04Interdomain routing, e.g. hierarchical routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/02Details
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression

Similar Documents

Publication Publication Date Title
Liu et al. Low cost fault-tolerant routing algorithm for networks-on-chip
Chen et al. Path-diversity-aware fault-tolerant routing algorithm for network-on-chip systems
Lotfi-Kamran et al. EDXY–A low cost congestion-aware routing algorithm for network-on-chips
Liu et al. Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead
Ahmed et al. Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Kohler et al. Fault tolerant network on chip switching with graceful performance degradation
Ebrahimi et al. MD: minimal path-based fault-tolerant routing in on-chip networks
Ebrahimi et al. Minimal-path fault-tolerant approach using connection-retaining structure in networks-on-chip
Ahmed et al. Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems
Killian et al. Smart reliable network-on-chip
Rahmani et al. High-performance and fault-tolerant 3D NoC-bus hybrid architecture using ARB-NET-based adaptive monitoring platform
Pasricha et al. NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults
Imai et al. Improving dependability and performance of fully asynchronous on-chip networks
Silveira et al. Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs
Hsin et al. Ant colony optimization-based fault-aware routing in mesh-based network-on-chip systems
Ahmed et al. Deadlock-recovery support for fault-tolerant routing algorithms in 3d-noc architectures
Ren et al. A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration
Ren et al. Fault-aware load-balancing routing for 2D-mesh and torus on-chip network topologies
Akbar et al. A novel adaptive congestion-aware and load-balanced routing algorithm in networks-on-chip
Pratomo et al. Gradient—An adaptive fault-tolerant routing algorithm for 2D mesh network-on-chips
Kuo et al. Path-diversity-aware adaptive routing in network-on-chip systems
Taheri et al. Advertiser elevator: A fault tolerant routing algorithm for partially connected 3D Network-on-Chips
Kia et al. A new fault-tolerant and congestion-aware adaptive routing algorithm for regular networks-on-chip
Neishaburi et al. NISHA: A fault-tolerant NoC router enabling deadlock-free interconnection of subnets in hierarchical architectures
Shafiei et al. Development of an adaptive multipath routing algorithm by examining the congestion and channel fault of one-hop nodes in network-on-chip