Sootkaneung et al., 2021 - Google Patents
Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit VariationsSootkaneung et al., 2021
View PDF- Document ID
- 11217747466169950268
- Author
- Sootkaneung W
- Chookaew S
- Howimanporn S
- Publication year
- Publication venue
- 2021 IEEE 30th Asian Test Symposium (ATS)
External Links
Snippet
While supply voltage and frequency directly affect circuit soft errors, thermal response from tuning these two parameters also provides a moderate side effect. This study firstly improves the accuracy of logic soft error estimation by taking into consideration the thermal impact …
- 230000000116 mitigating 0 title abstract description 12
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Wirnshofer | Variation-aware adaptive voltage scaling for digital CMOS circuits | |
Frustaci et al. | Analytical delay model considering variability effects in subthreshold domain | |
Butzen et al. | Leakage current in sub-micrometer cmos gates | |
Lorenzo et al. | LCNT-an approach to minimize leakage power in CMOS integrated circuits | |
Romli et al. | An overview of power dissipation and control techniques in cmos technology | |
Salamin et al. | Minimizing excess timing guard banding under transistor self-heating through biasing at zero-temperature coefficient | |
Sootkaneung et al. | Thermal effect on performance, power, and BTI aging in FinFET-based designs | |
Sengupta et al. | Generalized power-delay metrics in deep submicron CMOS designs | |
Sootkaneung et al. | Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations | |
Ma et al. | Key characterization factors of accurate power modeling for FinFET circuits. | |
Mottaghi et al. | Aging mitigation in FPGAs considering delay, power, and temperature | |
Calimera et al. | Temperature-Insensitive Dual-$ V_ {\rm th} $ Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence | |
AKM et al. | Circuit techniques for device-circuit interaction toward minimum energy operation | |
Sharma et al. | Effective drive current for near-threshold CMOS circuits’ performance evaluation: Modeling to circuit design techniques | |
Maryan et al. | A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22ánm CMOS process | |
Calimera et al. | Power-gating for leakage control and beyond | |
Sootkaneung et al. | Combined impact of BTI and temperature effect inversion on circuit performance | |
Guo et al. | Design and aging challenges in FinFET circuits and internet of things (IoT) applications | |
Singh et al. | Design and lifetime estimation of low-power 6-Input Look-Up table used in Modern FPGA | |
Stangherlin | Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling | |
Ghosh et al. | Aspects of low-power high-speed CMOS VLSI design: A review | |
Dokić et al. | Low-voltage low-power CMOS design | |
Shah et al. | LISOCHIN: An NBTI degradation monitoring sensor for reliable CMOS circuits | |
Ramkrishna et al. | Analysis of NBTI Impact on Clock Path Duty Cycle Degradation | |
Rosa et al. | Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability |