Popat et al., 2018 - Google Patents
Hardware Security in Case of Scan Based Attack on Crypto HardwarePopat et al., 2018
View PDF- Document ID
- 1087485949607630709
- Author
- Popat J
- Mehta U
- Publication year
- Publication venue
- International Journal of VLSI design & Communication Systems (VLSICS) Vol
External Links
Snippet
The latest innovation technology in computing devices has given a rise of compact, speedy and economical products which also embeds cryptography hardware on-chip. This device generally holds secret key and confidential information, more attention has been given to …
- 238000004458 analytical method 0 abstract description 20
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Krautter et al. | Active fences against voltage-based side channels in multi-tenant FPGAs | |
Da Rolt et al. | Test versus security: Past and present | |
Canivet et al. | Glitch and laser fault attacks onto a secure AES implementation on a SRAM-based FPGA | |
Lin et al. | Trojan side-channels: Lightweight hardware trojans through side-channel engineering | |
Cui et al. | Static and dynamic obfuscations of scan data against scan-based side-channel attacks | |
Da Rolt et al. | Are advanced DfT structures sufficient for preventing scan-attacks? | |
Rolt et al. | A novel differential scan attack on advanced DFT structures | |
Liu et al. | Scan-based attacks on linear feedback shift register based stream ciphers | |
Chiu et al. | A secure test wrapper design against internal and boundary scan attacks for embedded cores | |
Das et al. | PUF-based secure test wrapper design for cryptographic SoC testing | |
Yasin et al. | Testing the trustworthiness of IC testing: An oracle-less attack on IC camouflaging | |
Dupuis et al. | New testing procedure for finding insertion sites of stealthy hardware Trojans | |
Atobe et al. | Secure scan design with dynamically configurable connection | |
Ege et al. | Differential scan attack on AES with X-tolerant and X-masked test response compactor | |
Da Rolt et al. | A scan-based attack on elliptic curve cryptosystems in presence of industrial design-for-testability structures | |
Vaghani et al. | On securing scan design through test vector encryption | |
Becker et al. | Implementing hardware trojans: Experiences from a hardware trojan challenge | |
Inoue et al. | Partial scan approach for secret information protection | |
Sao et al. | Co-relation scan attack analysis (COSAA) on AES: A comprehensive approach | |
Chen et al. | Partial scan design against scan-based side channel attacks | |
Chen et al. | Balancing testability and security by configurable partial scan design | |
Chen et al. | Scan chain based IP fingerprint and identification | |
Popat et al. | Hardware Security in Case of Scan Based Attack on Crypto Hardware | |
Popat et al. | A novel countermeasure against differential scan attack in AES algorithm | |
Shao et al. | Fast and automatic security test on cryptographic ICs against fault injection attacks based on design for security test |