Colnarič et al., 1992 - Google Patents
Architectural support for predictability in hard real-time systemsColnarič et al., 1992
- Document ID
- 10705901857289968283
- Author
- Colnarič M
- Halang W
- Publication year
- Publication venue
- IFAC Proceedings Volumes
External Links
Snippet
There is evidence that, among all design domains of hard real time systems, architectural issues gained the lowest research interest. Universal architectures, which are generally applied as hardware bases for hard real time applications, are seldom behaving in a fully …
- 238000000034 method 0 abstract description 18
Classifications
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- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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- G—PHYSICS
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- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
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- G06F9/5061—Partitioning or combining of resources
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- G—PHYSICS
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- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
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- G—PHYSICS
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- G06F9/44—Arrangements for executing specific programmes
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- G06F9/45533—Hypervisors; Virtual machine monitors
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- G—PHYSICS
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- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
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- G—PHYSICS
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