[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Alves et al., 2011 - Google Patents

Dynamic test set selection using implication-based on-chip diagnosis

Alves et al., 2011

View PDF
Document ID
10751757801828090162
Author
Alves N
Shi Y
Imbriglia N
Dworak J
Nepal K
Bahar R
Publication year
Publication venue
2011 Sixteenth IEEE European Test Symposium

External Links

Snippet

We propose using logic implications as a source of online diagnostic data for on-chip test set selection by taking advantage of their ability to automatically identify a restricted set of faults as the potential cause of an observed error. This information will be used to dynamically …
Continue reading at scholar.archive.org (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices

Similar Documents

Publication Publication Date Title
Reddy et al. Compact test sets for high defect coverage
US8006152B2 (en) Scan chain fail diagnostics
Pomeranz Computation of seeds for LFSR-based diagnostic test generation
US10605863B2 (en) Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits
US20090222779A1 (en) Methods and apparatuses for generating a random sequence of commands for a semiconductor device
US11237210B1 (en) Layout-aware test pattern generation and fault detection
Alves et al. Dynamic test set selection using implication-based on-chip diagnosis
Amyeen et al. A joint diagnostic test generation procedure with dynamic test compaction
US20100274518A1 (en) Diagnostic Test Pattern Generation For Small Delay Defect
EP1526459A3 (en) Improved method for diagnosing complex system faults
Pomeranz LFSR-based test generation for path delay faults
US9194916B2 (en) Method with system and program product for prioritizing clock domains for testing of integrated circuit designs
US9557383B2 (en) Partitioned scan chain diagnostics using multiple bypass structures and injection points
US20100097072A1 (en) System and method for checking analog circuit with digital checker
Pomeranz Test and non-test cubes for diagnostic test generation based on merging of test cubes
Zhang et al. Cost-driven optimization of coverage of combined built-in self-test/automated test equipment testing
Pomeranz et al. TOV: sequential test generation by ordering of test vectors
Pomeranz Non-Uniform Coverage by $ n $-Detection Test Sets
US9372771B1 (en) Method of grouping embedded memories for testing
Pomeranz et al. On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit
Pomeranz Diagnostic test generation that addresses diagnostic holes
US9429621B2 (en) Implementing enhanced scan chain diagnostics via bypass multiplexing structure
Addepalli et al. Using fault detection tests to produce diagnostic tests targeting large sets of candidate faults
Pomeranz et al. Generation of broadside transition-fault test sets that detect four-way bridging faults
Pomeranz et al. Test sequences to achieve high defect coverage for synchronous sequential circuits