Bi et al., 2017 - Google Patents
Cross-layer optimization for multilevel cell STT-RAM cachesBi et al., 2017
View PDF- Document ID
- 10613585233164224479
- Author
- Bi X
- Mao M
- Wang D
- Li H
- Publication year
- Publication venue
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
External Links
Snippet
Spin-transfer torque random access memory (STT-RAM), as an emerging nonvolatile memory technology, provides very dense array structure and extremely low leakage power consumption. It demonstrates a great potential in replacing conventional static random …
- 238000005457 optimization 0 title abstract description 16
Classifications
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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