Mock et al., 2005 - Google Patents
An empirical study of data speculation use on the intel itanium 2 processorMock et al., 2005
View PDF- Document ID
- 10355687905051415973
- Author
- Mock M
- Villamarin R
- Baiocchi J
- Publication year
- Publication venue
- 9th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT'05)
External Links
Snippet
The Intel Itanium architecture uses a dedicated 32-entry hardware table, the advanced load address table (ALAT) to support data speculation via an instruction set interface. This study presents an empirical evaluation of the use of the ALAT and data speculative instructions for …
- 238000011156 evaluation 0 abstract description 3
Classifications
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- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
- G06F9/3842—Speculative instruction execution
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- G—PHYSICS
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- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G06F8/44—Encoding
- G06F8/443—Optimisation
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- G06F8/4442—Reducing the number of cache misses; Data prefetching
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