[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Pan et al., 2015 - Google Patents

Design of a Low‐Power 20Gb/s 1: 4 Demultiplexer in 0.18 μm CMOS

Pan et al., 2015

View PDF @Full View
Document ID
10121958517012027089
Author
Pan M
Feng J
Publication year
Publication venue
Chinese Journal of Electronics

External Links

Snippet

A low‐power multi‐phase clock 20Gb/s 1: 4 Demultiplexer (DEMUX) without inductors is designed in 0.18 μm Complementary metal oxide semiconductor (CMOS) process. The 1: 4 DEMUX includes two 1: 2 DEMUX cells, one 1/2 frequency divider cell, some data and clock …
Continue reading at ietresearch.onlinelibrary.wiley.com (PDF) (other versions)

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices using field-effect transistors
    • H03K17/693Switching arrangements with several input- or output-terminals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines

Similar Documents

Publication Publication Date Title
Jung et al. A 25-gb/s 5-mw cmos cdr/deserializer
Abiri et al. A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS
Hafez et al. A 32–48 Gb/s serializing transmitter using multiphase serialization in 65 nm CMOS technology
Knapp et al. 25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12/spl mu/m CMOS
CN104702285B (en) A kind of analog-digital converter and D conversion method
Tsai et al. A novel low gate-count pipeline topology with multiplexer-flip-flops for serial link
Fukaishi et al. A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture
Yang et al. A one-wire approach for skew-compensating clock distribution based on bidirectional techniques
Pan et al. Design of a Low‐Power 20Gb/s 1: 4 Demultiplexer in 0.18 μm CMOS
CN101917194A (en) Double-edge triggering high-speed digital-to-analog converter
Chien et al. A 15-Gb/s 2: 1 multiplexer in 0.18-μm CMOS
US20200127645A1 (en) High-speed transmitter including a multiplexer using multi-phase clocks
Zhang et al. A novel CML latch for ultra high speed applications
Maeda et al. An ultralow-power-consumption, high-speed, GaAs 256/258 dual-modulus prescaler IC
Tondo et al. A low-power, high-speed CMOS/CML 16: 1 serializer
Chang et al. A 32-mw 40-gb/s cmos nrz transmitter
Ali et al. 45 GHz low power static frequency divider in 90 nm CMOS
Kehrer et al. A 30-gb/s 70-mW one-stage 4: 1 multiplexer in 0.13-/spl mu/m CMOS
Kjellberg et al. 104Gb/s 2"-1 and 110Gb/s 2-1 PRBS Generator in InP HBT Technology
Mineyama et al. A 20 Gb/s 1: 4 DEMUX with near-rail-to-rail logic swing in 90 nm CMOS process
Lao et al. A 12 Gb/s Si bipolar 4: 1-multiplexer IC for SDH systems
CN201774516U (en) Double-edge triggering high-speed digital-to-analog converter
Min et al. A low power 12Gb/s 1: 4 demultiplexer in 0.18 μm CMOS
Sekiguchi et al. Inductorless 8.9 mW 25 Gb/s 1: 4 DEMUX and 4 mW 13 Gb/s 4: 1 MUX in 90 nm CMOS
Sekiguchi et al. An 8.9 mW 25Gb/s inductorless 1: 4 DEMUX in 90nm CMOS