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Mertens et al., 2017 - Google Patents

Gate-all-around transistors based on vertically stacked Si nanowires

Mertens et al., 2017

Document ID
9762210650141670764
Author
Mertens H
Ritzenthaler R
Hikavyy A
Kim M
Tao Z
Wostyn K
Schram T
Kunnen E
Ragnarsson L
Dekkers H
Hopf T
Devriendt K
Tsvetanova D
Chew S
Kikuchi Y
Van Besien E
Rosseel E
Mannaert G
De Keersgieter A
Chasin A
Kubicek S
Dangol A
Demuynck S
Barla K
Mocuta D
Horiguchi N
Publication year
Publication venue
ECS Transactions

External Links

Snippet

We report on gate-all-around (GAA) N-and P-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process …
Continue reading at iopscience.iop.org (other versions)

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