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Bolotin et al., 2007 - Google Patents

The power of priority: NoC based distributed cache coherency

Bolotin et al., 2007

View PDF
Document ID
9611342896813840751
Author
Bolotin E
Guz Z
Cidon I
Ginosar R
Kolodny A
Publication year
Publication venue
First International Symposium on Networks-on-Chip (NOCS'07)

External Links

Snippet

The paper introduces network-on-chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance chip multi processors (CMPs). We address previously proposed CMP architectures based on non …
Continue reading at ran.net.technion.ac.il (PDF) (other versions)

Classifications

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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
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