Ammar et al., 2017 - Google Patents
System-level analysis of the vulnerability of processors exposed to single-event upsets via probabilistic model checkingAmmar et al., 2017
- Document ID
- 8983514103849178361
- Author
- Ammar M
- Hamad G
- Mohamed O
- Savaria Y
- Publication year
- Publication venue
- IEEE Transactions on Nuclear Science
External Links
Snippet
Due to current technology scaling trends, digital designs are becoming strongly susceptible to space radiation effects. These effects can cause unwanted single-event upsets (SEUs) in any state element. This paper presents a new system-level model of SEUs propagation …
- 238000004458 analytical method 0 title abstract description 24
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Leveugle et al. | Statistical fault injection: Quantified error and confidence | |
Li et al. | Accurate microarchitecture-level fault modeling for studying hardware faults | |
Piscitelli et al. | Fault attacks, injection techniques and tools for simulation | |
Papadimitriou et al. | Silent data corruptions: Microarchitectural perspectives | |
Papadimitriou et al. | Avgi: Microarchitecture-driven, fast and accurate vulnerability assessment | |
Ammar et al. | Towards an accurate probabilistic modeling and statistical analysis of temporal faults via temporal dynamic fault-trees (TDFTs) | |
Parasyris et al. | A framework for evaluating software on reduced margins hardware | |
Ammar et al. | System-level analysis of the vulnerability of processors exposed to single-event upsets via probabilistic model checking | |
Chen et al. | Formal quantification of the register vulnerabilities to soft error in RTL control paths | |
Plusquellic et al. | Information leakage analysis using a co-design-based fault injection technique on a risc-v microprocessor | |
Anzt et al. | Tuning stationary iterative solvers for fault resilience | |
Kriebel et al. | ACSEM: Accuracy-configurable fast soft error masking analysis in combinatorial circuits | |
Rivers et al. | Phaser: Phased methodology for modeling the system-level effects of soft errors | |
Andraus et al. | CEGAR-based formal hardware verification: A case study | |
Spruyt | Building fault models for microcontrollers | |
Ammar et al. | Comprehensive vulnerability analysis of systems exposed to seus via probabilistic model checking | |
Blackstone et al. | A unified model for gate level propagation analysis | |
Ammar et al. | System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs) | |
Xue et al. | Using formal methods to evaluate hardware reliability in the presence of soft errors | |
Azambuja et al. | The limitations of software signature and basic block sizing in soft error fault coverage | |
Dammak et al. | SEU Reliability Assessment Framework for COTS Many-core Processors | |
Velazco et al. | Robustness with respect to SEUs of a self-converging algorithm | |
Elmohr | Embedded systems security: On em fault injection on risc-v and br/tbr puf design on fpga | |
Lee | Fault sensitivity analysis of a 32-bit RISC microprocessor | |
Köylü et al. | Instruction flow-based detectors against fault injection attacks |