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Hu et al., 2021 - Google Patents

Developing Formal Models for Measuring Fault Effects Using Functional EDA Tools

Hu et al., 2021

View PDF
Document ID
8947441886117538677
Author
Hu W
Tan J
Wu L
Tai Y
Hong L
Publication year
Publication venue
2021 IEEE International Test Conference in Asia (ITC-Asia)

External Links

Snippet

State-of-the-art EDA tools largely employ functional circuit models that are inadequate for verifying and emulating design properties related to fault effect and tolerance. In this paper, we derive fully synthesizable fault effect propagation models for formally reasoning about …
Continue reading at cf-hk.aconf.org (PDF) (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
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    • G01R31/317—Testing of digital circuits
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    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
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    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

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