[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Metra et al., 1997 - Google Patents

On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits

Metra et al., 1997

Document ID
8921908642007629420
Author
Metra C
Favalli M
Olivo P
Ricco B
Publication year
Publication venue
IEEE transactions on computer-aided design of integrated circuits and systems

External Links

Snippet

This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • G06F17/5031Timing analysis
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/504Formal methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3668Software testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. varying supply voltage
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression

Similar Documents

Publication Publication Date Title
US6931611B2 (en) Design verification system for avoiding false failures and method therefor
Abraham et al. Fault and error models for VLSI
US6378112B1 (en) Verification of design blocks and method of equivalence checking of multiple design views
Asadi et al. An analytical approach for soft error rate estimation in digital circuits
US6996515B1 (en) Enabling verification of a minimal level sensitive timing abstraction model
Breuer The effects of races, delays, and delay faults on test generation
Hamad et al. Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits
Tamir et al. Design and application of self-testing comparators implemented with MOS PLA's
Shazli et al. Using boolean satisfiability for computing soft error rates in early design stages
Metra et al. On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
Wakerly Partially self-checking circuits and their use in performing logical operations
US10768227B2 (en) Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device
Ashar et al. Exploiting multi-cycle false paths in the performance optimization of sequential circuits
Westerman et al. Discrete event system approach for delay fault analysis in digital circuits
Metra et al. Embedded two-rail checkers with on-line testing ability
Firdous et al. Speeding up of design convergence using spyglass
Metra et al. On-line testing of transient faults affecting functional blocks of FCMOS, domino and FPGA-implemented self-checking circuits
Nanya et al. The byzantine hardware fault model
Kazma et al. Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis
Kavousianos et al. Self-exercising self testing k-order comparators
Metra et al. Design rules for CMOS self checking circuits with parametric faults in the functional block
Kaja et al. Metfi: Model-driven fault simulation framework
Metra et al. Signal coding technique and CMOS gates for strongly fault-secure combinational functional blocks
Hamad et al. Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL
Acken et al. Part 1: Logic circuit simulation