Catthoor et al., 2020 - Google Patents
Scenarios in dataflow modeling and analysisCatthoor et al., 2020
View PDF- Document ID
- 8911761888649283940
- Author
- Catthoor F
- Basten T
- Zompakis N
- Geilen M
- Kjeldsberg P
- Geilen M
- Skelin M
- van Kampenhout J
- Ara H
- Basten T
- Stuijk S
- Goossens K
- Publication year
- Publication venue
- System-scenario-based design principles and applications
External Links
Snippet
Dataflow models can be used to model and program concurrent systems and applications. Static timed dataflow models commonly abstract the temporal behavior of systems in terms of their worst-case behaviors. This may lead to models that are very pessimistic. The …
- 238000004458 analytical method 0 title abstract description 77
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06Q—DATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
- G06Q10/06—Resources, workflows, human or project management, e.g. organising, planning, scheduling or allocating time, human or machine resources; Enterprise planning; Organisational models
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Thoen et al. | Modeling, verification and exploration of task-level concurrency in real-time embedded systems | |
Singh et al. | Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs | |
Manolache et al. | Task mapping and priority assignment for soft real-time applications under deadline miss ratio constraints | |
Geilen et al. | Performance analysis of weakly-consistent scenario-aware dataflow graphs | |
Casale-Brunet | Analysis and optimization of dynamic dataflow programs | |
Marzolla | Simulation-based performance modeling of UML software architectures. | |
Ziegenbein et al. | Combining multiple models of computation for scheduling and allocation | |
Chadli et al. | High-level frameworks for the specification and verification of scheduling problems | |
Skelin et al. | Model checking of finite-state machine-based scenario-aware dataflow using timed automata | |
Kumar et al. | Analyzing composability of applications on MPSoC platforms | |
Indrusiak et al. | Dynamic resource allocation in embedded, high-performance and cloud computing | |
Catthoor et al. | Scenarios in dataflow modeling and analysis | |
McGee et al. | Efficient performance analysis of asynchronous systems based on periodicity | |
Castrillon et al. | Dataflow Models of computation for programming heterogeneous multicores | |
Szemethy et al. | Platform Modeling and Model Transformations for Analysis. | |
Cortadella et al. | Quasi-static scheduling of independent tasks for reactive systems | |
Shen et al. | Serial-equivalent static and dynamic parallel routing for FPGAs | |
Geilen et al. | Kahn process networks and a reactive extension | |
Chadli et al. | A model-based framework for the specification and analysis of hierarchical scheduling systems | |
Schaumont et al. | Data flow modeling and transformation | |
Bhattacharyya et al. | Model-based representations for dataflow schedules | |
Desnos et al. | Dataflow modeling for reconfigurable signal processing systems | |
Tripakis et al. | Tokens vs. signals: On conformance between formal models of dataflow and hardware | |
Prihozhy et al. | Evaluation of the parallelization potential for efficient multimedia implementations: dynamic evaluation of algorithm critical path | |
An et al. | High-level design space exploration for adaptive applications on multiprocessor systems-on-chip |