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Wächter et al., 2016 - Google Patents

A hierarchical and distributed fault tolerant proposal for NoC-based MPSoCs

Wächter et al., 2016

View PDF
Document ID
8574626861658455045
Author
Wächter E
Fochi V
Barreto F
Amory A
Moraes F
Publication year
Publication venue
IEEE Transactions on Emerging Topics in Computing

External Links

Snippet

Aggressive scaling of CMOS process technology allows the fabrication of highly integrated chips such as NoC-based MPSoCs. However, fault probability increases when devices' size reduces. Hence, fault tolerant design has an important role in current nanometric …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
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    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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