[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Ganguly et al., 1996 - Google Patents

PowerPC/sup (TM)/array verification methodology using formal techniques

Ganguly et al., 1996

Document ID
8331641268600821847
Author
Ganguly N
Abadir M
Pandey M
Publication year
Publication venue
Proceedings International Test Conference 1996. Test and Design Validity

External Links

Snippet

In this paper we discuss the methodology used on PowerPC RISC microprocessors to verify the correctness of embedded array blocks. The functional behavior of these blocks cannot be verified using traditional functional simulators since the search space is too large. Our …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring

Similar Documents

Publication Publication Date Title
Devadas et al. An observability-based code coverage metric for functional simulation
Civera et al. Exploiting circuit emulation for fast hardness evaluation
US20070050740A1 (en) Method and System for Performing Functional Formal Verification of Logic Circuits
US20080127009A1 (en) Method, system and computer program for automated hardware design debugging
US20080126068A1 (en) Accelerated simulation and verification of a system under test (sut) using cache and replacement management tables
Gai et al. MOZART: a concurrent multilevel simulator
US20090064071A1 (en) Method and system for global coverage analysis
Pandey et al. Formal verification of PowerPC arrays using symbolic trajectory evaluation
Corno et al. Automatic test bench generation for validation of RT-level descriptions: an industrial experience
Ganguly et al. PowerPC/sup (TM)/array verification methodology using formal techniques
US5796990A (en) Hierarchical fault modeling system and method
US20070005323A1 (en) System and method of automating the addition of programmable breakpoint hardware to design models
US5859962A (en) Automated verification of digital design
US6510405B1 (en) Method and apparatus for selectively displaying signal values generated by a logic simulator
Bombieri et al. Incremental ABV for functional validation of TL-to-RTL design refinement
US7194715B2 (en) Method and system for performing static timing analysis on digital electronic circuits
US20020072889A1 (en) Efficient array tracing in a logic simulator machine
US20070005322A1 (en) System and method for complex programmable breakpoints using a switching network
Krishnamurthy et al. Validating PowerPC microprocessor custom memories
Chang et al. A biased random instruction generation environment for architectural verification of pipelined processors
Baraona et al. VSPEC: A declarative requirements specification language for VHDL
US6813599B1 (en) Efficient memory structure simulation for sequential circuit design verification
Blank et al. Symbolic simulation techniques-state-of-the-art and applications
Segev et al. Evaluating and comparing simulation verification vs. formal verification approach on block level design
Suryasarman et al. Rsbst: an accelerated automated software-based self-test synthesis for processor testing