Ali et al., 2016 - Google Patents
Parallelization of unit propagation algorithm for SAT-based ATPG of digital circuitsAli et al., 2016
- Document ID
- 8102237931345036272
- Author
- Ali L
- Hussein A
- Ali H
- Publication year
- Publication venue
- 2016 28th International Conference on Microelectronics (ICM)
External Links
Snippet
The recent enhancements in Boolean Satisfiability solving has made SAT solvers a core engine for many real world applications especially for Automatic Test Pattern Generation (ATPG) in digital circuits. The majority of solving time is spent on iteratively propagating …
- 101710003518 ATPAF2 0 title description 4
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N5/00—Computer systems utilising knowledge based models
- G06N5/02—Knowledge representation
- G06N5/022—Knowledge engineering, knowledge acquisition
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Järvisalo et al. | Blocked clause elimination | |
Tsai et al. | State of B\" uchi Complementation | |
US20140157218A1 (en) | Model-based retiming with functional equivalence constraints | |
Hahanov et al. | Information analysis infrastructure for diagnosis | |
Kiesl et al. | Super-blocked clauses | |
Ali et al. | Parallelization of unit propagation algorithm for SAT-based ATPG of digital circuits | |
Disch et al. | Combinational equivalence checking using incremental SAT solving, output ordering, and resets | |
Gaber et al. | Computation of minimal unsatisfiable subformulas for SAT-based digital circuit error diagnosis | |
Wimmer et al. | Skolem functions for DQBF | |
Seidl et al. | Partial witnesses from preprocessed quantified Boolean formulas | |
Jas et al. | An approach to minimizing functional constraints | |
Possani et al. | Parallel combinational equivalence checking | |
Ciesielski et al. | Function extraction from arithmetic bit-level circuits | |
Chang et al. | Post-placement rewiring and rebuffering by exhaustive search for functional symmetries | |
Sabharwal | SymChaff: A structure-aware satisfiability solver | |
Ubar et al. | Structural fault collapsing by superposition of BDDs for test generation in digital circuits | |
Ali et al. | An efficient computation of minimal correction subformulas for SAT-based ATPG of digital circuits | |
Nadeem et al. | Polynomial formal verification of adder circuits using answer set programming | |
Li et al. | A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism | |
Wimmer et al. | Analysis of incomplete circuits using dependency quantified Boolean formulas | |
Siládi et al. | Adapted parallel Quine-McCluskey algorithm using GPGPU | |
Safarpour et al. | Improved SAT-based reachability analysis with observability don’t cares | |
McMillan | Don't-care computation using k-clause approximation | |
Chen et al. | SMT Solver With Hardware Acceleration | |
Lu et al. | SEChecker: A Sequential Equivalence Checking Framework Based on ${K} $ th Invariants |