Cracraft et al., 2014 - Google Patents
Unintended effects of asymmetric return vias and via array design for reduced mode conversionCracraft et al., 2014
- Document ID
- 8064574389037560489
- Author
- Cracraft M
- Connor S
- Archambeault B
- Publication year
- Publication venue
- 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)
External Links
Snippet
Return path discontinuities have been shown to have significant impact on high speed signals. Along with gaps in reference structures, return via placement can adversely affect signal integrity and radiated emissions. Of specific concern is mode conversion, often …
- 238000006243 chemical reaction 0 title abstract description 55
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5077—Routing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, and noise or electromagnetic interference
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/16—Constructional details or arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11675954B2 (en) | Method of designing a device | |
US8288657B2 (en) | Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules | |
US7350175B2 (en) | Circuit board design system, design data analysis method and recording medium with analysis program recorded thereon | |
US20170148492A1 (en) | Memory card | |
US11076493B2 (en) | Implementing high-speed signaling via dedicated printed circuit-board media | |
US20060253819A1 (en) | Design checks for signal lines | |
US7367003B2 (en) | System and method for verifying trace lengths and trace spaces in a circuit | |
US10263380B2 (en) | Crosstalk reduction in electrical interconnects | |
US7765504B2 (en) | Design method and system for minimizing blind via current loops | |
JP2019096857A (en) | High speed differential trace with reduced radiation in return path | |
Erdin et al. | Decoupling capacitor placement on resonant parallel-plates via driving point impedance | |
CN101389183A (en) | Through-hole region design system and method for differential signal line | |
JPWO2006121042A1 (en) | Method, apparatus, and program for creating power supply model of semiconductor integrated circuit | |
US20090276745A1 (en) | Dummy metal insertion processing method and apparatus | |
US20140189190A1 (en) | Mechanism for facilitating dynamic cancellation of signal crosstalk in differential input/output channels | |
US9379424B2 (en) | Compensation for length differences in vias associated with differential signaling | |
Cracraft et al. | Unintended effects of asymmetric return vias and via array design for reduced mode conversion | |
Zhao et al. | Decoupling capacitor power ground via layout analysis for multi-layered PCB PDNs | |
Jaze et al. | Differential mode to common mode conversion on differential signal vias due to asymmetric GND via configurations | |
Wang et al. | Capacitance calculation for via structures using an integral equation method based on partial capacitance | |
US20100251200A1 (en) | Via design apparatus and via design method | |
Bai et al. | Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk | |
US20210161011A1 (en) | Circuit substrate, chip, series circuit, circuit board and electronic device | |
Cracraft et al. | Return via location optimization to minimize mode conversion in differential via transitions | |
Kong et al. | Guided Interconnect-The Next-Generation Flex Circuits for High-Performance System Design |