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Ulm et al., 1998 - Google Patents

Simulating PRAM with a MSIMD model (ASC)

Ulm et al., 1998

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Document ID
7181092311446970792
Author
Ulm D
Baker J
Publication year
Publication venue
Proceedings. 1998 International Conference on Parallel Processing (Cat. No. 98EX205)

External Links

Snippet

The ASC (MSIMD) model for parallel computation supports a generalized version of an associative style of computing that has been used since the introduction of associative SIMD computers in the early 1970's. In particular, this model supports data parallelism, constant …
Continue reading at www.cs.kent.edu (PDF) (other versions)

Classifications

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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
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    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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    • G06F9/46—Multiprogramming arrangements
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    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
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    • G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
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    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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