[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Thomas et al., 2007 - Google Patents

High quality uniform random number generation using LUT optimised state-transition matrices

Thomas et al., 2007

View PDF
Document ID
714533253052088504
Author
Thomas D
Luk W
Publication year
Publication venue
The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

External Links

Snippet

This paper presents a family of uniform random number generators designed for efficient implementation in Lookup table (LUT) based FPGA architectures. A generator with a period of 2 k− 1 can be implemented using k flip-flops and k LUTs, and provides k random output …
Continue reading at cas.ee.ic.ac.uk (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/582Pseudo-random number generators
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724Finite field arithmetic
    • G06F7/726Inversion; Reciprocal calculation; Division of elements of a finite field
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219Countermeasures against side channel or fault attacks
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass

Similar Documents

Publication Publication Date Title
Thomas et al. High quality uniform random number generation using LUT optimised state-transition matrices
Bakiri et al. Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses
Thomas et al. The LUT-SR family of uniform random number generators for FPGA architectures
Guan et al. Pseudorandom number generation with self-programmable cellular automata
Duong-Ngoc et al. Area-efficient number theoretic transform architecture for homomorphic encryption
Derya et al. CoHA-NTT: A configurable hardware accelerator for NTT-based polynomial multiplication
Nguyen et al. High-level synthesis in implementing and benchmarking number theoretic transform in lattice-based post-quantum cryptography using software/hardware codesign
Gupta et al. Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
Palchaudhuri et al. Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
Silitonga et al. Hls-based performance and resource optimization of cryptographic modules
Imran et al. High-speed SABER key encapsulation mechanism in 65nm CMOS
Soni et al. Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow
Galli et al. On the effectiveness of true random number generators implemented on FPGAs
Kamadi et al. Implementation of TRNG with SHA-3 for hardware security
Alaghi et al. Accuracy and correlation in stochastic computing
Thomas et al. High quality uniform random number generation through LUT optimised linear recurrences
Echeverría et al. High performance FPGA-oriented mersenne twister uniform random number generator
Tan et al. ThundeRiNG: Generating multiple independent random number sequences on FPGAs
Bakiri Hardware implementation of a pseudo random number generator based on chaotic iteration
Addabbo et al. Efficient implementation of pseudochaotic piecewise linear maps with high digitization accuracies
Ibrahim Systolic processor core for finite-field multiplication and squaring in cryptographic processors of iot edge devices
Sasao et al. Decomposition of index generation functions using a Monte Carlo method
Rezaei Shahmirzadi et al. Energy Consumption of Protected Cryptographic Hardware Cores: An Experimental Study
Saraf et al. A memory optimized mersenne-twister random number generator
Duke-Bergman et al. Evaluating the performance of FPGA-based secure hash algorithms for use in SPHINCS+