Yan et al., 2014 - Google Patents
A reconfigurable processor architecture combining multi-core and reconfigurable processing unitsYan et al., 2014
- Document ID
- 7104854047747298063
- Author
- Yan L
- Wu B
- Wen Y
- Zhang S
- Chen T
- Publication year
- Publication venue
- Telecommunication Systems
External Links
Snippet
It'sa promising way to improve performance significantly by adding reconfigurable processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi- Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed …
- 238000004891 communication 0 abstract description 25
Classifications
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- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
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- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
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