[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Cheng et al., 2000 - Google Patents

The design and implementation of DCT/IDCT chip with novel architecture

Cheng et al., 2000

View PDF
Document ID
7087003231974650401
Author
Cheng K
Huang C
Lin C
Publication year
Publication venue
2000 IEEE International Symposium on Circuits and Systems (ISCAS)

External Links

Snippet

In the paper, an efficient VLSI architecture for a 8/spl times/8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes sure all coefficients …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/14Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/147Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/14Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141Discrete Fourier transforms
    • G06F17/142Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding, overflow
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • G06F17/16Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16Constructional details or arrangements

Similar Documents

Publication Publication Date Title
Jia et al. A new VLSI-oriented FFT algorithm and implementation
Chang et al. An efficient pipelined FFT architecture
Huang et al. CORDIC based fast radix-2 DCT algorithm
Guo et al. An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization
Han et al. A novel area-power efficient design for approximated small-point FFT architecture
Cheng et al. The design and implementation of DCT/IDCT chip with novel architecture
Coelho et al. DFT computation using gauss-eisenstein basis: FFT algorithms and VLSI architectures
Heyne et al. A computationally efficient high-quality cordic based DCT
Chen et al. VLSI implementation of a 16* 16 DCT
Sung et al. High-efficiency and low-power architectures for 2-D DCT and IDCT based on CORDIC rotation
Shabani et al. Area and power-efficient variable-sized DCT architecture for HEVC using Muxed-MCM problem
Mukherjee et al. Hardware efficient architecture for 2D DCT and IDCT using Taylor-series expansion of trigonometric functions
Coelho et al. Computation of 2D 8× 8 DCT based on the Loeffler factorization using algebraic integer encoding
An et al. Recursive algorithm, architectures and FPGA implementation of the two-dimensional discrete cosine transform
Takala et al. Butterfly unit supporting radix-4 and radix-2 FFT
Sakellariou et al. Application-specific low-power multipliers
Chiang et al. A high throughput 2-dimensional DCT/IDCT architecture for real-time image and video system
He et al. Efficient FPGA design for Convolutions in CNN based on FFT-pruning
Yang et al. Approximate computing based low power image processing architecture for intelligent satellites
Chen et al. A high-throughput and area-efficient video transform core with a time division strategy
Mamatha et al. Hybrid architecture for sinusoidal and non-sinusoidal transforms
More et al. FPGA implementation of FFT processor using vedic algorithm
Sung Memory-efficient and high-performance 2-D DCT and IDCT processors based on CORDIC rotation
Huang et al. A novel VLSI linear array for 2-D DCT/IDCT
Zhang et al. Design of an efficient multiplier-less architecture for multi-dimensional convolution