[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

SULAIMAN et al., 2019 - Google Patents

The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling

SULAIMAN et al., 2019

View PDF
Document ID
6716140827312832619
Author
SULAIMAN D
HAMARASH I
IBRAHIM M
Publication year
Publication venue
ZANCO Journal of Pure and Applied Sciences

External Links

Snippet

The modern CPU technology scaling with increasing transistor density causes an exponential growth of both dynamic and static power dissipations that affecting the microprocessor's performance. The body bias voltage (VBB) and supply voltage (VDD) …
Continue reading at conferences.su.edu.krd (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3287Power saving by switching off individual functional units in a computer system, i.e. selective power distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3296Power saving by lowering supply or operating voltage
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3237Power saving by disabling clock generation or distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/324Power saving by lowering clock frequency
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details

Similar Documents

Publication Publication Date Title
Kawai et al. A fully static topologically-compressed 21-transistor flip-flop with 75% power saving
Dreslinski et al. Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits
Pu et al. A 9-mm 2 ultra-low-power highly integrated 28-nm CMOS SoC for Internet of Things
US7782110B1 (en) Systems and methods for integrated circuits comprising multiple body bias domains
Kao et al. A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture
Yamaoka et al. A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
US20020113616A1 (en) Semiconductor integrated circuit
Bol et al. SleepRunner: A 28-nm FDSOI ULP cortex-M0 MCU with ULL SRAM and UFBR PVT compensation for 2.6–3.6-μW/DMIPS 40–80-MHz active mode and 131-nW/kB fully retentive deep-sleep mode
Varadharajan et al. Low power VLSI circuits design strategies and methodologies: A literature review
Chen et al. Assessment of circuit optimization techniques under NBTI
Consoli et al. Novel class of energy-efficient very high-speed conditional push–pull pulsed latches
Uytterhoeven et al. A sub 10 pJ/cycle over a 2 to 200 MHz performance range RISC-V microprocessor in 28 nm FDSOI
Kosonocky et al. Low-power circuits and technology for wireless digital systems
Kanno et al. Hierarchical power distribution with power tree in dozens of power domains for 90-nm low-power multi-CPU SoCs
US20130038382A1 (en) Adjustable body bias circuit
Okuhara et al. Digitally assisted on-chip body bias tuning scheme for ultra low-power VLSI systems
Shiomi et al. Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing
SULAIMAN et al. The Complete Switching Circuit Design for CPU Joint Body Biasing and Supply Voltage Scaling
Chowdhury et al. Innovative power gating for leakage reduction
Sengupta et al. Power-delay metrics revisited for 90 nm CMOS technology
AKM et al. Circuit techniques for device-circuit interaction toward minimum energy operation
Beigné et al. Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes
Ghosh et al. A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation
Campi Power-Shaping Configurable Microprocessors for IoT Devices
Borkar Extreme energy efficiency by near threshold voltage operation