Durna et al., 2011 - Google Patents
On board data handling subsystem featuring BiLGEDurna et al., 2011
- Document ID
- 630608329369598497
- Author
- Durna M
- Atar O
- Ceylan M
- Cakmakci Y
- Demirci M
- Kozal Ă
- Oturak M
- Ă–zdemir A
- Turhan O
- Uzay T
- Publication year
- Publication venue
- Proceedings of 5th International Conference on Recent Advances in Space Technologies-RAST2011
External Links
Snippet
TÜBITAK UZAY LEO mission RASAT that has a planned launch in June 2011 employs an on-board data handling system to support for a 7m PAN-15m MS imaging payload together with a couple of experimental payloads of which one is BiLGE, a new on-board computer to …
- 210000004279 Orbit 0 abstract description 6
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10338560B2 (en) | Two-way architecture with redundant CCDL's | |
WO2018120442A1 (en) | Multi-task master control system for remote sensing satellite image processing load | |
US8484509B2 (en) | Radiation-hardened processing system | |
CN107077103B (en) | Bidirectional architecture | |
US20110078498A1 (en) | Radiation-hardened hybrid processor | |
US20110099421A1 (en) | Radiation-hardened hybrid processor | |
Wilson et al. | CSP hybrid space computing for STP-H5/ISEM on ISS | |
US7840852B2 (en) | Method and system for environmentally adaptive fault tolerant computing | |
Eickhoff | Combined Data and Power Management Infrastructure | |
EP0883838B1 (en) | Shared bw architecture for applications with varying levels of integrity requirements | |
Durna et al. | On board data handling subsystem featuring BiLGE | |
Johnson et al. | Fault tolerant computer system for the A129 helicopter | |
Amorim et al. | Dependable MPSoC framework for mixed criticality applications | |
Botma | The Design and Development of an ADCS OBC for a CubeSat | |
US11023249B1 (en) | First stage bootloader (FSBL) | |
Ramos et al. | High-performance, dependable multiprocessor | |
Eickhoff | System Design Concept | |
Lindsay et al. | Open-Source Flight Computer Platform for CubeSats | |
McCabe et al. | Avionics architecture interface considerations between constellation vehicles | |
Behr et al. | Fault tolerance and COTS: next generation of high performance satellite computers | |
Shin et al. | A software-based monitoring framework for time-space partitioned avionics systems | |
Kazi et al. | Design and Validation Architecture of the Dream Chaser® Fault Tolerant Flight Computer | |
Yuehua et al. | Distributed storage system for satellite platform based on SpaceWire network: SpaceWire missions and applications, short paper | |
Seagrave | Spacecube: A reconfigurable processing platform for space | |
Pertuz et al. | A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing |