Vafaei et al., 2024 - Google Patents
HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate ComputingVafaei et al., 2024
View PDF- Document ID
- 6148017988395998031
- Author
- Vafaei J
- Akbari O
- Publication year
- Publication venue
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Snippet
For critical applications that require a higher level of reliability, the triple modular redundancy (TMR) scheme is usually employed to implement fault-tolerant arithmetic units. However, this method imposes a significant area and power/energy overhead. Also, the …
- 238000013461 design 0 abstract description 58
Classifications
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- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
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- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
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