[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Kong et al., 2000 - Google Patents

Data-dependent evaluating latched CMOS differential logic family for statistical power reduction

Kong et al., 2000

Document ID
588693150826003106
Author
Kong B
Jun Y
Publication year
Publication venue
2000 IEEE International Symposium on Circuits and Systems (ISCAS)

External Links

Snippet

In this paper, a novel CMOS differential logic family, called data-dependent evaluating latched CMOS logic (DELL), is proposed for use in low-power VLSI. The proposed logic family discharges internal precharge nodes on demand, and thus, statistically reduces the …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096Synchronous circuits, i.e. using clock signals
    • H03K19/0963Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356104Bistable circuits using complementary field-effect transistors
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/012Modifications of generator to improve response time or to decrease power consumption
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used

Similar Documents

Publication Publication Date Title
EP1592133B1 (en) N-domino output latch with accelerated evaluate path
US5796282A (en) Latching mechanism for pulsed domino logic with inherent race margin and time borrowing
US5828234A (en) Pulsed reset single phase domino logic
US6977528B2 (en) Event driven dynamic logic for reducing power consumption
EP1868291B1 (en) N-domino register with accelerated non-discharge path
US5920218A (en) Single-phase edge-triggered dual-rail dynamic flip-flop
US5523707A (en) Fast, low power exclusive or circuit
US6060927A (en) High-speed D flip-flop
US6693459B2 (en) Method and system for improving speed in a flip-flop
US6781411B2 (en) Flip flop with reduced leakage current
US20040100307A1 (en) Circuit for asychronous reset in current mode logic circuits
US6191618B1 (en) Contention-free, low clock load domino circuit topology
US20050083082A1 (en) Retention device for a dynamic logic stage
US5642061A (en) Short circuit current free dynamic logic clock timing
US6646487B2 (en) Method and system for reducing hazards in a flip-flop
US5821775A (en) Method and apparatus to interface monotonic and non-monotonic domino logic
EP1868292B1 (en) P-domino register with accelerated non-charge path
US6646474B2 (en) Clocked pass transistor and complementary pass transistor logic circuits
US7193445B2 (en) Non-inverting domino register
US7187211B2 (en) P-domino output latch
US6542006B1 (en) Reset first latching mechanism for pulsed circuit topologies
US6466057B1 (en) Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method
Kong et al. Data-dependent evaluating latched CMOS differential logic family for statistical power reduction
Lee et al. Split-level precharge differential logic: A new type of high-speed charge-recycling differential logic
JPH06350430A (en) Circuit and method for operating it