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Ienne et al., 1994 - Google Patents

Bit-serial multipliers and squarers

Ienne et al., 1994

View PDF
Document ID
5307594091580298790
Author
Ienne P
Viredaz M
Publication year
Publication venue
IEEE Transactions on Computers

External Links

Snippet

Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are …
Continue reading at citeseerx.ist.psu.edu (PDF) (other versions)

Classifications

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