Moghaddasi et al., 2018 - Google Patents
Instruction-level NBTI stress estimation and its application in runtime aging prediction for embedded processorsMoghaddasi et al., 2018
- Document ID
- 5248264147052893199
- Author
- Moghaddasi I
- Fouman A
- Salehi M
- Kargahi M
- Publication year
- Publication venue
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
External Links
Snippet
Lifetime reliability management of miniaturized CMOS devices continuously gets more importance with the shrinking of technology size. Neither of existing design-time solutions (like guard-banding) and runtime methods (like reactive monitoring) does efficiently address …
- 230000032683 aging 0 title abstract description 97
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3296—Power saving by lowering supply or operating voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/16—Constructional details or arrangements
- G06F1/20—Cooling means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/86—Event-based monitoring
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Coskun et al. | Proactive temperature management in MPSoCs | |
Henkel et al. | Reliable on-chip systems in the nano-era: Lessons learnt and future trends | |
Coskun et al. | Proactive temperature balancing for low cost thermal management in MPSoCs | |
Xie et al. | APOLLO: An automated power modeling framework for runtime power introspection in high-volume commercial microprocessors | |
Sengupta et al. | Estimating circuit aging due to BTI and HCI using ring-oscillator-based sensors | |
Khoshavi et al. | Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods | |
Firouzi et al. | Aging-and variation-aware delay monitoring using representative critical path selection | |
Kim et al. | Energy and lifetime optimizations for dark silicon manycore microprocessor considering both hard and soft errors | |
Firouzi et al. | Statistical analysis of BTI in the presence of process-induced voltage and temperature variations | |
Moghaddasi et al. | Instruction-level NBTI stress estimation and its application in runtime aging prediction for embedded processors | |
Hong et al. | Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability | |
US20130211752A1 (en) | Software power analysis | |
Kumar et al. | Machine learning based workload balancing scheme for minimizing stress migration induced aging in multicore processors | |
Moghaddasi et al. | Aging-aware instruction-level statistical dynamic timing analysis for embedded processors | |
US9477568B2 (en) | Managing interconnect electromigration effects | |
Zhang et al. | HAT-DRL: Hotspot-aware task mapping for lifetime improvement of multicore system using deep reinforcement learning | |
Lerner et al. | Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors | |
Vijayan et al. | Machine learning-based aging analysis | |
Wang et al. | On the simulation of NBTI-induced performance degradation considering arbitrary temperature and voltage variations | |
Oboril et al. | Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC EJ McCluskey doctoral thesis award competition finalist | |
Kothawade et al. | Analysis of intermittent timing fault vulnerability | |
Firouzi et al. | Adaptive fault-tolerant DVFS with dynamic online AVF prediction | |
Listl et al. | Emulation of an ASIC power, temperature and aging monitor system for FPGA prototyping | |
Zandian et al. | Cross-layer resilience using wearout aware design flow | |
Jung et al. | A stochastic local hot spot alerting technique |