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Oberman et al., 1994 - Google Patents

Design issues in floating-point division

Oberman et al., 1994

View PDF
Document ID
5144473235234800852
Author
Oberman S
Flynn M
Publication year
Publication venue
Technical Report CSL-TR-94–647

External Links

Snippet

Floating-point division is generally regarded as a low frequency, high latency operation in typical oating-point applications. However, the increasing emphasis on high performance graphics and the industry-wide usage of performance benchmarks, such as SPECmarks …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G06F7/52—Multiplying; Dividing
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    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
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