[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Zachariah et al., 2003 - Google Patents

Algorithm to extract two-node bridges

Zachariah et al., 2003

Document ID
4932472273463798256
Author
Zachariah S
Chakravarty S
Publication year
Publication venue
IEEE transactions on very large scale integration (VLSI) systems

External Links

Snippet

Current bridge fault extraction techniques are limited by performance and capacity constraints. In this paper, we present a fast and accurate algorithm to extract and rank two- node bridges based on the computation of their weighted critical area. Experimental results …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99942—Manipulating data structure, e.g. compression, compaction, compilation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06Q—DATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00—Administration; Management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing

Similar Documents

Publication Publication Date Title
Jyu et al. Statistical timing analysis of combinational logic circuits
Vemuri et al. BDD-based logic synthesis for LUT-based FPGAs
US6480816B1 (en) Circuit simulation using dynamic partitioning and on-demand evaluation
Xiong et al. Criticality computation in parameterized statistical timing
Najm et al. CREST-a current estimator for CMOS circuits.
KR20120047336A (en) Hierarchical order ranked simulation of electronic circuits
Pan et al. Optimal clock period clustering for sequential circuits with retiming
US6732340B1 (en) Method for designing a semiconductor integrated circuit which includes consideration of parasitic elements on critical data paths
Zachariah et al. Algorithm to extract two-node bridges
US20010020289A1 (en) Modifying timing graph to avoid given set of paths
Zhang et al. Speeding up vlsi layout verification using fuzzy attributed graphs approach
US6507807B1 (en) Method and apparatus for determining which branch of a network of an integrated circuit has the largest total effective RC delay
Daseking et al. Vista: a VLSI CAD system
Meyer et al. Active timing multilevel fault-simulation with switch-level accuracy
Kao Piecewise linear models for switch level simulation
Jouppi Timing verification and performance improvement of MOS VLSI designs
JPH07287051A (en) Input data creation device for logic simulation
Tsai et al. Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
Neves et al. Automated Synthesis of Skew‐Based Clock Distribution Networks
Tong et al. Performance-driven register insertion in placement
US6275970B1 (en) Evaluation of the design quality of network nodes
Heineken SIMSTRAD: silicon implementation strategy advisor
US20040225979A1 (en) Method for identifying removable inverters in an IC design
Stamenković Algorithm for extracting integrated circuit critical areas associated with point defects
JP3152184B2 (en) Device simulation method