[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Ortega-Cisneros, 2023 - Google Patents

Design and implementation of an noc-based convolution architecture with gemm and systolic arrays

Ortega-Cisneros, 2023

Document ID
4884059076258491044
Author
Ortega-Cisneros S
Publication year
Publication venue
IEEE Embedded Systems Letters

External Links

Snippet

Neural networks have been used for a long time for image detection and recognition applications due to their ability and efficiency in complex problem solving. Several researchers have chosen to design and develop hardware accelerators for the convolution …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/80Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061Partitioning or combining of resources
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/109Switching fabric construction integrated on microchip, e.g. switch-on-chip
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computer systems based on biological models
    • G06N3/02Computer systems based on biological models using neural network models
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10Complex mathematical operations
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/06Deflection routing, e.g. hot-potato routing

Similar Documents

Publication Publication Date Title
Liu et al. Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems
CN110516801A (en) A High Throughput Dynamically Reconfigurable Convolutional Neural Network Accelerator Architecture
WO2020133317A1 (en) Computing resource allocation technology and neural network system
Arka et al. ReGraphX: NoC-enabled 3D heterogeneous ReRAM architecture for training graph neural networks
CN101834789B (en) Packet-circuit exchanging on-chip router oriented rollback steering routing algorithm and router used thereby
CN103345461A (en) Multi-core processor on-chip network system based on FPGA and provided with accelerator
Firuzan et al. Reconfigurable network-on-chip for 3D neural network accelerators
WO2020133463A1 (en) Neural network system and data processing technology
CN102497411A (en) Intensive operation-oriented hierarchical heterogeneous multi-core on-chip network architecture
Reza et al. Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks
Haghi et al. A reconfigurable compute-in-the-network fpga assistant for high-level collective support with distributed matrix multiply case study
CN116861966B (en) Transformer model accelerator and construction and data processing methods and devices thereof
Wang et al. Network-on-interposer design for agile neural-network processor chip customization
Sun et al. Multi-node acceleration for large-scale GCNs
Joseph et al. NEWROMAP: Mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI
Akbari et al. A high-performance network-on-chip topology for neuromorphic architectures
Ortega-Cisneros Design and implementation of an noc-based convolution architecture with gemm and systolic arrays
Bhowmik et al. ESCA: Event-based split-CNN architecture with data-level parallelism on ultrascale+ FPGA
Ding et al. A hybrid-mode on-chip router for the large-scale FPGA-based neuromorphic platform
US20220058468A1 (en) Field Programmable Neural Array
Ouyang et al. URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators
Bui et al. A scalable network-on-chip based neural network implementation on FPGAs
Chen et al. Dynamic mapping mechanism to compute DNN models on a resource-limited NoC platform
CN114723029A (en) DCNN accelerator based on hybrid multi-row data flow strategy
Liu et al. Energy-efficient and low-latency optical network-on-chip architecture and mapping solution for artificial neural networks