Shelar et al. - Google Patents
Pass Transistor Logic Synthesizer (PTLS)Shelar et al.
View HTML- Document ID
- 4822089306510745699
- Author
- Shelar R
- Sapatnekar S
External Links
Snippet
Pass transistor logic (PTL) offers a good area/power-delay trade-off alternative to static CMOS circuits in today's technologies. It may continue to do so even when leakage power becomes dominant in sub-100 nano-meter era due to smaller area implementations as …
- 230000015572 biosynthetic process 0 abstract description 8
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5077—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Eles et al. | System synthesis with VHDL | |
US6785875B2 (en) | Methods and apparatus for facilitating physical synthesis of an integrated circuit design | |
KR100296183B1 (en) | Design method of semiconductor integrated circuit, semiconductor integrated circuit and operation circuit | |
Melham | Abstraction mechanisms for hardware verification | |
US7020855B2 (en) | Digital circuit layout techniques using identification of input equivalence | |
US5680332A (en) | Measurement of digital circuit simulation test coverage utilizing BDDs and state bins | |
US20050268258A1 (en) | Rule-based design consultant and method for integrated circuit design | |
JP2005517223A (en) | Method for generating design constraints for modules of hierarchical integrated circuit design system | |
Shepard et al. | Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors | |
Lin et al. | Power reduction by gate sizing with path-oriented slack calculation | |
Lis et al. | VHDL synthesis using structured modeling | |
US6654936B2 (en) | Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit | |
US6305003B1 (en) | System and method for propagating clock nodes in a netlist of circuit design | |
US6367055B1 (en) | Method and apparatus for determining certain characteristics of circuit elements | |
Shelar et al. | Pass Transistor Logic Synthesizer (PTLS) | |
US5682519A (en) | Method for reducing power consumption of switching nodes in a circuit | |
US7437695B1 (en) | Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices | |
US6502223B1 (en) | Method for simulating noise on the input of a static gate and determining noise on the output | |
US6542860B1 (en) | System and method for detecting nodes that are susceptible to floating | |
Abednazari et al. | BAS: A BTI-based aging aware synthesis in FPGAs | |
US6295632B1 (en) | System and method for detecting the output of a clock driver | |
Frosssl et al. | A new model to uniformly represent the function and timing of MOS circuits and its application to VHDL simulation | |
Kelem et al. | Context-based ASIC synthesis | |
Goeders et al. | Power aware architecture exploration for field programmable gate arrays | |
Seomun et al. | Skewed flip-flop transformation for minimizing leakage in sequential circuits |