Fritzmann et al., 2020 - Google Patents
RISQ-V: Tightly coupled RISC-V accelerators for post-quantum cryptographyFritzmann et al., 2020
View PDF- Document ID
- 4812920323562675586
- Author
- Fritzmann T
- Sigl G
- Sepúlveda J
- Publication year
- Publication venue
- IACR Transactions on Cryptographic Hardware and Embedded Systems
External Links
Snippet
Empowering electronic devices to support Post-Quantum Cryptography (PQC) is a challenging task. PQC introduces new mathematical elements and operations which are usually not easy to implement on standard processors. Especially for low cost and resource …
- 230000015654 memory 0 abstract description 52
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
- G06F7/726—Inversion; Reciprocal calculation; Division of elements of a finite field
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Fritzmann et al. | RISQ-V: Tightly coupled RISC-V accelerators for post-quantum cryptography | |
Alkim et al. | ISA Extensions for Finite Field Arithmetic Accelerating Kyber and NewHope on RISC-V. | |
Zhang et al. | Highly efficient architecture of NewHope-NIST on FPGA using low-complexity NTT/INTT | |
Banerjee et al. | Sapphire: A configurable crypto-processor for post-quantum lattice-based protocols | |
Fritzmann et al. | Masked accelerators and instruction set extensions for post-quantum cryptography | |
Zhu et al. | LWRpro: An energy-efficient configurable crypto-processor for module-LWR | |
Fritzmann et al. | Towards reliable and secure post-quantum co-processors based on RISC-V | |
Zhao et al. | A compact and high-performance hardware architecture for CRYSTALS-Dilithium | |
Jiang et al. | Matcha: A fast and energy-efficient accelerator for fully homomorphic encryption over the torus | |
Dang et al. | High-speed hardware architectures and FPGA benchmarking of CRYSTALS-Kyber, NTRU, and Saber | |
Zhou et al. | A software/hardware co-design of crystals-dilithium signature scheme | |
Duong-Ngoc et al. | Area-efficient number theoretic transform architecture for homomorphic encryption | |
Feldmann et al. | F1: A fast and programmable accelerator for fully homomorphic encryption (extended version) | |
Derya et al. | CoHA-NTT: A configurable hardware accelerator for NTT-based polynomial multiplication | |
Mert et al. | Medha: Microcoded hardware accelerator for computing on encrypted data | |
Cousins et al. | An update on SIPHER (scalable implementation of primitives for homomorphic encryption)—FPGA implementation using Simulink | |
Wang et al. | Efficient implementation of Dilithium signature scheme on FPGA SoC platform | |
Aikata et al. | A unified cryptoprocessor for lattice-based signature and key-exchange | |
Bisheh-Niasar et al. | A monolithic hardware implementation of Kyber: Comparing apples to apples in PQC candidates | |
Nejatollahi et al. | Domain-specific accelerators for ideal lattice-based public key protocols | |
Zhu et al. | A high-performance hardware implementation of saber based on Karatsuba algorithm | |
Mao et al. | High-performance and configurable SW/HW co-design of Post-Quantum Signature CRYSTALS-Dilithium | |
Ye et al. | A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications | |
Li et al. | A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber | |
Di Matteo et al. | CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms |