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Raghunathan et al., 1995 - Google Patents

Acceleration techniques for dynamic vector compaction

Raghunathan et al., 1995

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Document ID
4248204565017004769
Author
Raghunathan A
Chakradhar S
Publication year
Publication venue
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

External Links

Snippet

We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly improve the computation times without adversely affecting the quality of test sets …
Continue reading at websrv.cecs.uci.edu (PDF) (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
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    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
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    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
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    • G01R31/318583—Design for test
    • G01R31/318586—Design for test with partial scan or non-scannable parts
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    • G01R31/318558—Addressing or selecting of subparts of the device under test
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    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318385—Random or pseudo-random test pattern
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    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
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    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression

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