[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Kwiat et al., 1995 - Google Patents

Modeling a versatile FPGA for prototyping adaptive systems

Kwiat et al., 1995

View PDF
Document ID
4051304821559428007
Author
Kwiat K
Debany W
Hariri S
Publication year
Publication venue
Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype

External Links

Snippet

Currently, the Computer-Aided Engineering (CAE) environments for designing Field- Programmable Gate Arrays (FPGAs) do not support the simulation of FPGA reprogrammability, hence prototyping of adaptive systems relies upon using the actual …
Continue reading at citeseerx.ist.psu.edu (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5027—Logic emulation using reprogrammable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5018—Computer-aided design using simulation using finite difference methods or finite element methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/86—Hardware-Software co-design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/68—Processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Similar Documents

Publication Publication Date Title
US6035106A (en) Method and system for maintaining hierarchy throughout the integrated circuit design process
US5940603A (en) Method and apparatus for emulating multi-ported memory circuits
Trimberger A reprogrammable gate array and applications
Compton et al. Configuration relocation and defragmentation for run-time reconfigurable computing
US7260794B2 (en) Logic multiprocessor for FPGA implementation
US6178541B1 (en) PLD/ASIC hybrid integrated circuit
US20030105617A1 (en) Hardware acceleration system for logic simulation
EP0871223A1 (en) Process for the prototyping of mixed signal applications and field programmable system on a chip for applying said process
KR20030016210A (en) Method for implementing a physical design for a dynamically reconfigurable logic circuit
US8248869B1 (en) Configurable memory map interface and method of implementing a configurable memory map interface
Schewel A hardware/software co-design system using configurable computing technology
Tessier et al. The virtual wires emulation system: A gate-efficient ASIC prototyping environment
US8082139B1 (en) Displaying signals of a design block emulated in hardware co-simulation
Gupta Hardware-software codesign
US8600722B1 (en) Method and apparatus for providing program-based hardware co-simulation of a circuit design
US7703054B2 (en) Circuit emulation and debugging method
Kwiat et al. Modeling a versatile FPGA for prototyping adaptive systems
Fawcett Tools to speed FPGA development
JP2006268873A (en) Hardware acceleration system for functional simulation
JP3212709B2 (en) Logic simulation device
Drayer et al. A development system for creating real-time machine vision hardware using field programmable gate arrays
Xiang et al. Parameterized design and formal verification of multi-ported memory
Sklyarov et al. Integrated development environment for logic synthesis based on dynamically reconfigurable FPGAs
Esteves et al. EDgAR: A Platform for Hardware/Software Codesign
Ballagh et al. Java debug hardware models using jbits