[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Sharma et al., 2018 - Google Patents

Extension of EMPSIJ for estimating the impact of substrate noise on jitter in a CMOS inverter

Sharma et al., 2018

Document ID
4031300090525255470
Author
Sharma V
Tripathi J
Shrimali H
Publication year
Publication venue
2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

External Links

Snippet

This paper presents an analysis of jitter in a CMOS inverter due to power supply, ground bounce and substrate noise. The analysis is based on the recently introduced method EMPSIJ [1] which is extended in this paper for substrate noise induced jitter. To estimate …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00323Delay compensation
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices using field-effect transistors
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/16Modifications for eliminating interference voltages or currents
    • H03K17/161Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass
    • H03K5/01Shaping pulses
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements

Similar Documents

Publication Publication Date Title
US8476940B2 (en) Stress reduced cascoded CMOS output driver circuit
US7994821B1 (en) Level shifter circuits and methods
US9306553B2 (en) Voltage level shifter with a low-latency voltage boost circuit
US8947135B2 (en) Output circuit and voltage signal output method
CN111756363B (en) Apparatus and method for reducing output skew and transition delay of level shifter
RU2604054C1 (en) Voltage level converter
Waltari et al. Bootstrapped switch without bulk effect in standard CMOS technology
Tripathi et al. An analysis of power supply induced jitter for a voltage mode driver in high speed serial links
US6556040B2 (en) Method and apparatus for non-linear termination of a transmission line
Sharma et al. Extension of EMPSIJ for estimating the impact of substrate noise on jitter in a CMOS inverter
US20070046354A1 (en) Delay adjustment circuit and synchronous semiconductor device having the delay adjustment circuit
Chakraborty et al. Analysis of noise margin of CMOS inverter in sub-threshold regime
US20030189448A1 (en) MOSFET inverter with controlled slopes and a method of making
Strak et al. Analysis of timing jitter in inverters induced by power-supply noise
Wang et al. A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process
Tolbert et al. Accurate buffer modeling with slew propagation in subthreshold circuits
US8344782B2 (en) Method and apparatus to limit circuit delay dependence on voltage for single phase transition
US20140300386A1 (en) Voltage level shifter circuit, system, and method for high speed applications
US9118320B2 (en) Input buffer with current control mechanism
Figueiredo et al. Predicting noise and jitter in CMOS inverters
Darapu et al. Analysis of jitter in clock distribution networks
Bansal et al. A novel low power keeper technique for pseudo domino logic
Alioto et al. Nanometer MCML gates: models and design considerations
US7400172B2 (en) Miller capacitance tolerant buffer element
Filanovsky et al. Decomposition of drain current in weak, moderate, and strong inversion components