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Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of \(512 \times 512\) Frames

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Abstract

Motion estimation accounts for major part of the computational complexity of any video coding standard. In this paper, we present efficient VLSI architecture for the implementation of hexagonal search algorithm for fast motion estimation. The proposed architecture employs sequential processing of pixel data rather than parallel processing in order to reduce the hardware area substantially while achieving the real-time speed. A novel on-chip memory organization is proposed, which reduces the address generation complexity and helps improve the speed. The architecture when implemented in Verilog HDL and mapped to Virtex-5 FPGA achieves a maximum frequency of 340 MHz, while the gate count is calculated to be 3.1 K. Thus, the proposed architecture is considered suitable to be incorporated in commercial devices such as camcorders and smart phones.

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Authors and Affiliations

  1. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, 721302, West Bengal, India

    Rohan Mukherjee, Baishik Biswas, Indrajit Chakrabarti, Somnath Sengupta & Ajoy Kumar Ray

  2. Department of Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur, 721302, West Bengal, India

    Pranab Kumar Dutta

Authors
  1. Rohan Mukherjee
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  2. Baishik Biswas
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  3. Indrajit Chakrabarti
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  4. Pranab Kumar Dutta
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  5. Somnath Sengupta
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  6. Ajoy Kumar Ray
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Correspondence to Rohan Mukherjee.

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Mukherjee, R., Biswas, B., Chakrabarti, I. et al. Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of \(512 \times 512\) Frames. Circuits Syst Signal Process 36, 640–657 (2017). https://doi.org/10.1007/s00034-016-0315-6

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