Abstract
Symbolic trajectory evaluation (STE) is a model checking approach for efficient circuit verification. In the talk we follow the de-velopment of STE; from an ad-hoc use of symbolic simulation to a rich theory of model checking algorithms, inference rules, and abstraction verification techniques. In parallel, we discuss the development of a practical verification system based on STE with an emphasis on the impact on the system by actual use in an industrial setting.
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© 1998 Springer-Verlag Berlin Heidelberg
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Seger, CJ.H. (1998). Formal Methods in CAD from an Industrial Perspective. In: Gopalakrishnan, G., Windley, P. (eds) Formal Methods in Computer-Aided Design. FMCAD 1998. Lecture Notes in Computer Science, vol 1522. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49519-3_14
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DOI: https://doi.org/10.1007/3-540-49519-3_14
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