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Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers

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Abstract

Code generation for VLIW processors includes several optimization problems like code optimization, instruction scheduling, and register allocation. The high complexity of these problems usually does not allow the computation of the optimal solution. Instead, optimization techniques, e.g., based on heuristics, are used to find acceptable solutions in a reasonable time. List scheduling is a well known heuristic-based microcode compaction method, that bases its scheduling decisions on weights derived from dependency analysis of the input program. Additional information and methods have to be used in order to reach better code compaction. Also, more sophisticated code optimization and register allocation support better code compaction. In this paper, evolutionary algorithms are used as dynamic heuristics in code generation, which allows dynamic adaption to the given input program and target processor configuration. Three evolutionary algorithms for operation merging, instruction scheduling, and register allocation are presented and evaluated on an exemplary image processing application, which shows different processing characteristics in the subroutines. They outperform code generation based on static heuristics and allow compilation for restricted target architectures that cannot be handled by the static heuristics.

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Acknowledgements

This work was partly funded by the German Research Council (DFG) under project number PA 2762/2-1.

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  1. Institute of Microelectronic Systems, Leibniz Universität Hannover, Appelstraße 4, 30167, Hannover, Germany

    Florian Giesemann, Lukas Gerlach & Guillermo Payá-Vayá

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Correspondence to Guillermo Payá-Vayá.

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Giesemann, F., Gerlach, L. & Payá-Vayá, G. Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers. J Sign Process Syst 92, 655–678 (2020). https://doi.org/10.1007/s11265-019-01493-2

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